Computer Architecture Set 3

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Free Online Best Computer Architecture MCQ Questions for improve your basic knowledge of Computer Architecture. This Computer Architecture set 3 test that contains 25 Multiple Choice Questions with 4 options. You have to select the right answer to a question.

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Question 1

The two facilities provided by the debugger is __________

A	Trace points
B	Break points
C	Compile
D	Both Trace and Break points

Question 2

The I/O devices form the _____ of the tree structure.

A	Leaves
B	Subordinate roots
C	Left subtrees
D	Right subtrees

Question 3

The difference between DRAM’s and SDRAM’s is/are ________

A	The DRAM’s will not use the master slave relationship in data transfer
B	The SDRAM’s make use of clock
C	The SDRAM’s are more power efficient
D	None of Above

Question 4

The logical addresses generated by the cpu are mapped onto physical memory by ____________

A	Relocation register
B	TLB
C	MMU
D	None of Above

Question 5

The difference in the address and data connection between DRAM’s and SDRAM’s is _______

A	The usage of more number of pins in SDRAM’s
B	The requirement of more address lines in SDRAM’s
C	The usage of a buffer in SDRAM’s
D	None of Above

Question 6

The duration between the read and the mfc signal is ______

A	Access time
B	Latency
C	Delay
D	Cycle time

Question 7

The high speed mode of operation of the USB was introduced by _____

A	ANSI
B	ISA
C	USB 3.0
D	USB 2.0

Question 8

A _______ is used to restore the contents of the cells.

A	Sense amplifier
B	Refresh counter
C	Restorer
D	None of Above

Question 9

The Reason for the disregarding of the SRAM’s is ________

A	Low Efficiency
B	High power consumption
C	High Cost
D	All of the Above

Question 10

The transfer rate, when the USB is operating in low-speed of operation is _____

A	5 Mb/s
B	12 Mb/s
C	2.5 Mb/s
D	1.5 Mb/s

Question 11

The program used to find out errors is called __________

A	Debugger
B	Compiler
C	Assembler
D	Scanner

Question 12

The reason for the cells to lose their state over time is ________

A	The lower voltage levels
B	Usage of capacitors to store the charge
C	Use of Shift registers
D	None of Above

Question 13

The minimum time delay between two successive memory read operations is ______

A	Cycle time
B	Latency
C	Delay
D	None of Above

Question 14

The capacitors lose the charge over time due to ________

A	The leakage resistance of the capacitor
B	The small current in the transistor after being turned on
C	The defect of the capacitor
D	None of Above

Question 15

The disadvantage of DRAM over SRAM is/are _______

A	Lower data storage capacities
B	Higher heat dissipation
C	The cells are not static
D	All of the Above

Question 16

Which option is true regarding the carry in the ripple adders?

A	Are generated at the beginning only
B	Must travel through the configuration
C	Is generated at the end of each operation
D	None of Above

Question 17

The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________

A	Half adders
B	Full adders
C	Ripple adders
D	Fast adders

Question 18

__________ is the bottleneck, when it comes computer performance.

A	Memory access time
B	Memory cycle time
C	Delay
D	Latency

Question 19

The mode register is used to _______

A	Select the row or column data transfer mode
B	Select the mode of operation
C	Select mode of storing the data
D	All of Above

Question 20

The USB device follows _______ structure.

A	List
B	Huffman
C	Hash
D	Tree

Question 21

MFC is used to _________

A	Issue a read signal
B	Signal to the device that the memory read operation is complete
C	Signal the processor the memory operation is complete
D	Assign a device to perform the read operation

Question 22

In full adders the sum circuit is implemented using ________

A	And & or gates
B	NAND gate
C	XOR
D	XNOR

Question 23

The sampling process in speaker output is a ________ process.

A	Asynchronous
B	Synchronous
C	Isochronous
D	None of Above

Question 24

In trace mode of operation is ________

A	The program is interrupted after each detection
B	The program will not be stopped and the errors are sorted out after the complete program is scanned
C	There is no effect on the program, i.e the program is executed without rectification of errors
D	The program is halted only at specific points

Question 25

The logic operations are implemented using _______ circuits.

A	Bridge
B	Logical
C	Combinatorial
D	Gate

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